(A) Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) structure and method for preparing the same, and more particularly, to a dynamic random access memory structure having vertical floating body memory cells and method for preparing the same.
(B) Description of the Related Art
A memory cell of the DRAM generally consists of a metal oxide semiconductor field effect transistor and a capacitor on a silicon substrate, and the transistor includes a source electrode electrically connected to an upper storage plate of the capacitor. There are two types of capacitors: stack capacitors and deep trench capacitors. The stack capacitor is fabricated on the surface of the silicon substrate, while the deep trench capacitor is fabricated inside the silicon substrate. Recently, the integration of the DRAM has increased with the innovation of semiconductor fabrication technology rapidly. However, the size of the memory cell must be shrunk to achieve the purpose of high integration, i.e., increasing the integration needs to reduce the size of the transistor and the capacitor.
In 2002, Takahsi Ohasawa et al. discloses a new dynamic random access memory cell called floating body cell (FBC) (see: “Memory Design Using One-Transistor Gain Cell on SOI”, ISSCC Digest of Technical Paper, PP152-153). The floating body cell consists of a metal oxide semiconductor field effect transistor having a floating body on an expensive substrate of silicon on insulator (SOI), and the floating body serves to store carriers. Compared to the conventional one-transistor/one-capacitor memory cell using the capacitor to storing charges, the floating body cell stores the charges in the floating body without using an additional capacitor. Hence, the floating body cell has a simpler memory structure, smaller occupying area per memory cell and higher integration than the conventional one-transistor/one-capacitor memory cell.
Further, the conventional one-transistor/one-capacitor memory cell checks whether the stored data is “1” or “0” by comparing a read out voltage from the memory cell with a reference voltage. Comparatively, the floating body cell checks whether the stored data is “1” or “0” based on the magnitude of a read out current. However, the floating body cell stores the carriers around an interface between two different materials, and defects in the interface is likely to recombine with the carriers, which influences the retention time of the carriers in the floating body.